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Workshop: Physical Design not in Great Shape

From Electronic Engineering Times
April 22, 1996

By Nicolas Mokhoff

IC physical-design problems that pundits four years ago proclaimed "solved" brought some 120 experts back to the table here last week to address them anew. The Fifth Physical Design Workshop, sponsored by the Association for Computing Machinery's Special Interest Group on Design Automation, explored the chasm between circuit layout and circuit functions in the deep-submicron realm and concluded that a lack of focus, not tools, is what's holding the EDA industry back from closing the gap.

"The CAD-research community is solving yesterday's problems rather than tomorrow's," said Cadence Design Systems fellow Lou Scheffer, a veteran floor-planning and place-and-route-research specialist who spent two years as an IC designer. "We are wasting a lot of time improving things that are good enough while ignoring the things that will determine how we design in a few years.

"CAD people today are still concerned with finding a slightly better algorithm for some old problem, when they should be worrying about how in the world they are going to use 50 million transistors in any reasonable amount of time."

Physical interconnections delay will overtake gate delays as a design concern by the year 2000, mandating a shift in the physical design flow for deep-submicron, said Thomas Yin, vice president of the research group at workshop cosponsor Avant! Corp. The starting point, in Yin's view, should be timing-driven floor planning.

Physical constraints

"The other four steps in the flow follow as a result of the physical constraints imposed by deep-submicron design rules: timing-driven hierarchical place-and-route; physical timing optimization; parasitic extraction and delay calculation; and, finally, hierarchical verification," Yin said.

Manfred Wiesel, a design manager at Intel Corp.'s microprocessor group (Hillsboro, Ore.), offered a list of "creative tools," which he defines as tools that become more than incrementally better with each generation. Wiesel believes that clock routing and synthesis have begun to get creative and that floor planning -- with the exception of editing functions -- and cell synthesis are on the brink of creativity.

On the other hand, Wiesel said, some tools are actually declining in usefulness. Such tools as standard-cell synthesis/place-and-route and full-chip place-and-route were more useful five years ago than they are today, he said.

"The focus of EDA has been on ASICs, and the result is that creative tools have not kept up with submicron processes, increased clock speeds and electrical rules in today's full-custom designs," Wiesel said.

On his wish-list are tools whose output can be used without a large amount of iterations and editing; standardization of rules by such bodies as Sematech; standard interfaces; and, or course, EDA tools that run on Windows-based PCs.

Concurring with Intel

Concurring in some respects with the Intel position offered by Wiesel was Sun Microsystems Inc.'s Ultrasparc III CAD manager, Ward Vercruysse, who spent 11 years with various EDA vendors before joining Sun. Ward described today's high-speed design as a largely manual process. The CAD industry's major failing, he said, is that "Spice is still the only essential tool in the tool box." Vercruysse would like to see CAD tools for noise and crosstalk analysis, electromagnetic analysis, layout compaction, RLC extraction, transistor sizing and global composition.

In the essence, both the Intel and Sun wish-lists boiled down to this: Why can't the $1 billion EDA industry agree on standard practices to meet common challenges in building next-generation chips? David Lapotin of IBM Corp.'s Austin Research Center had this reply: "If you want to learn a lesson on how to manage tomorrow's design challenges, take a look at what Digital Equipment Corp's Alpha designers did. They meticulously went through all the needed physical design steps in a very purposeful manner, using tools they developed just for this mission. And the Alpha is still the highest-performance chip out there.

"So, if you're shooting for performance -- the bellwether of how CAD tools are developed -- you need to let tools be customizable for the respective design."

If it didn't decisively solve any problems, the workshop at least made some headway in pinpointing them and stressing the urgency of the need for solutions. "We gathered here because few, if any, of us can claim to know the real 'killer' issues in physical design," said Gabriel Robins, an assistant professor of computer science at the University of Virginia and the workshop's general chairman.

Technical program chairman Andrew Kahng, an associate professor of computer science at UCLA, added that the workshop planners had "hoped to raise the pertinent issues, such as 'What kind of problem will cause XYZ chip to miss its market window in 1999: timing, thermal, noise, algorithms or flows?' And to the extent that the majority of participants agreed that the search for answers must be drastically accelerated, we have succeeded with the workshop."

Advance the cause

One post-workshop effort that might advance the cause of standardization in at least one physical design domain -- partitioning -- is underway over the Internet. In an invitation to all research teams engaged in prototyping partitioning algorithms, Franc Brglez, director of the CAD Benchmarking Laboratory at North Carolina State University, is overseeing a Net-based partitioning contest that is hoped to yield a collaborative, peer-reviewed benchmarking process by yearend.


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